1. Field of the Invention
The invention relates generally to computer data storage systems, and more particularly to a flexible parity generation circuit for use with a redundant array of data storage units.
2. Description of the Prior Art
State-of-the-art computing systems generally employ CPUs and solid-state memories which operate at relatively high speeds compared with the typical I/O access times of data storage units, such as magnetic or optical disk drives. The performance capabilities of these CPUs and memories is not maximally utilized unless the speed of I/O data transfer operations is increased correspondingly. One technique of enhancing I/O data transfer speed involves the use of a plurality of data storage units, such that a plurality of these units may be accessed at a given moment.
Although the use of multiple data storage units increases the overall speed of I/O data transfer operations, this approach has one disadvantage. As the number of storage units increases, the mean-time-between-failure of the array of units decreases proportionately. Assuming a constant failure rate, such that time to failure is exponentially distributed, and further assuming that failures are independent, the mean time before failure of an array of storage units is equal to the mean time before failure of a single unit divided by the number of units in the array.
Utilization of large data storage unit arrays necessitates the employment of data backup or redundancy techniques to recover data if a storage unit fails. To overcome the reliability problem, storage unit configurations have been developed which use additional storage space to store redundancy information. In this manner, the original information may be recovered when a storage unit fails. One such storage unit configuration is referred to as RAID (Redundant Array of Inexpensive Disks). RAID systems typically store redundancy information in the form of data parity bytes.
FIG. 1 is a block diagram illustrating a typical prior-art computing system containing a central processing unit (CPU) 401, a buffer/controller 403, and a plurality of data storage units 404. The CPU 401 communicates with the buffer/controller 403 via a CPU bus 402, and the buffer/controller 403 communicates with the data storage units 404 via I/O buses 405. Also included in the system is a parity generation circuit 406. It is common for the speed of communications over the CPU bus 402 to be significantly faster than the speed of communications over the I/O buses 405. The I/O bus 405 speed is inherently limited by the data transfer times of the data storage units 404, whereas the CPU bus 402 speed is only limited by the gate delays of the electronic solid-state devices used in the CPU 401 and the buffer/controller 403, and the electrical properties of the physical bus conductors.
In a typical prior art computing system, the CPU bus 402 operates at about 40megabytes per second, whereas each I/O bus 405 operates at about only 6 megabytes per second. However, in the case where a plurality of data storage units 404 are employed, it would be desirable to increase the effective speed of the I/O buses 405 by accessing a plurality of data storage units 404 in an interleaved manner.
A typical process for initially generating redundancy information, such as data parity bytes, from existing data includes receiving a first block of data from the CPU 401, writing the data block to a storage unit 404, and copying the data block to an electronic memory device. A second related block of data is then received from the CPU 401, and written to a corresponding location on a next storage unit 404. Concurrently, the first and second blocks of data are fed (byte-by-byte or word-by-word) to respective first and second inputs of an exclusive-OR (XOR) gate within the parity generation circuit 406, such that each byte from the first data block is XOR'd with a corresponding byte from the second data block. The output of the XOR gate represents parity information. The parity information calculated from the first and second data blocks is placed into the electronic memory device. The process is repeated until all related data blocks from the CPU 401 have been XOR'd with the contents of the electronic memory device, producing a final parity block which may be written to a data storage unit.
After a parity block is initially generated for a series of related data blocks, the parity block is updated each time one of the related data blocks on a storage unit is changed. This process is known as a "Read-Modify-Write" operation. The Read-Modify-Write operation uses a well-known algorithm that reads an old parity block and an old data block, then XOR's the old parity block, the old data block, and a new data block within the parity generation circuit 406 to generate a new parity block. The new data block and the new parity block are then written over the corresponding old data block and old parity block on the respective storage units 404.
FIG. 2 is a block diagram illustrating in greater detail a prior art parity generation circuit 406 for generating parity information. In the example shown, data storage units 600-603 are employed in conjunction with a word-wide, first-in/first-out (FIFO) memory 604, a two-input, 36-bit wide XOR gate 605, a counter 606, a switch 607, a tri-state buffer 608, a buffered data controller 610, storage unit buses 630, 632, 634, and 636, and a system bus 640. (The width of the "word" in the preferred embodiment is 36-bits, comprising 32 bits of data and 4 bits of hardware bus parity information for each byte; these 4 bits are not part of the redundancy information stored on the data storage units 600-603). The system bus 640 is connected to buffer/control circuitry 609. The buffer/control circuitry 609 interfaces the system bus 640 with a high-speed (e.g., 40 MHz) CPU bus 641. The data storage units 600-603 are organized into a plurality of blocks, such as a1, a2, a3, and a4, comprising a first data "stripe", and b1, b2, b3 and b4, comprising a second data "stripe".
The system of FIG. 2 commences a Read-Modify-Write operation of the data in block a1 by accessing the "old" data in block a1 of data storage unit 600. This old data traverses the storage unit bus 630 at a relatively low transfer rate. The buffered data controller 610, which comprises a plurality of device controllers having buffer memories, interfaces the storage unit bus 630 with the system bus 640. The switch 607 routes the old data from block a1 to the FIFO 604 over a first data line 620. The counter 606 counts the number of words written into the FIFO 604 (a separate counter, not shown, that is part of a DMA controller within the bus interface circuitry block 609, counts the number of times a complete data block is processed through the parity generation circuit 406). Once the FIFO 604 is filled with the old data from block a1, the counter 606 inputs a signal to the switch 607. The signal causes the switch 607 to route subsequent data over a second line 624 directly to a first input of the XOR gate 605.
If the data in block a2 is the "old" parity information for the a1-a4 data "stripe", then the old parity data from block a2 is read from storage unit 601 and transmitted to the switch 607, which routes the old parity over data line 624 to the first input of the XOR gate 605. Simultaneous with the application of the parity block a2 to the first input of the XOR gate 605, the old data from the FIFO 604 is applied to the second input of the XOR gate 605, word-by-word, such that respective words from data block a1 are applied to the second input of the XOR gate 605 at the same time that corresponding words from parity block a2 are applied to the first input of the XOR gate 605. The output of the XOR gate 605 represents parity information for only data blocks a3 and a4 (i.e., the parity contribution of data block a1 has been subtracted out). The parity information thus generated is written back into the FIFO 604 over data line 626.
Thereafter, new data block a1', destined to be written over old block a1, is received on the CPU bus 641 from the CPU 401. The new data block is coupled to the system bus 640 by buffer/controller circuitry 609. As the new data block a1' is received, it is coupled via the buffered data controller 610 to the storage unit bus 630, and written over block a1. Concurrently, the new data block a1' is coupled via the switch 607 to the first input of the XOR gate 605, and XOR'd, word-by-word, with the partial parity information from the FIFO 604, thereby generating a new parity block a2' for the a1-a4 data stripe. The new parity block a2' is written back into the FIFO 604 over data line 626.
Once the external counter in the DMA controller within the bus interface circuitry block 609 indicates that the new parity block a2' has accumulated in the FIFO 604, that block is read under DMA control from the FIFO 604 and transmitted across data lines 622 and 628 to the tri-state buffer 608. Appropriate control signals are applied to the tri-state buffer 608, causing the buffer 608 to convey the new parity block a2' from the FIFO 604 to the system bus 640. The buffered data controller 610 receives the new parity block a2' and writes it to the corresponding data stripe of the allocated parity storage unit (here, block a2), thereby completing the Read-Modify-Write operation.
Although the above description uses 36-bit-wide (word-wide) portions of each block, the principles apply to any size width-unit of data, such as bit-wide or byte-wide.
The performance of present parity generation circuits of the type shown in FIG. 2 is limited by the maximum speed of the storage unit buses 630-636 relative to the CPU bus 641. Although the CPU bus 641 typically operates at about 40 MHz, the storage unit buses 630-636 operate at only about 6 MHz. Thus, the high-speed of the CPU bus 641 is not fully exploited. It would be very desirable to compensate for the disparity in the respective bus speeds so that the advantages of the higher speed CPU bus 641 could be fully realized.
What is needed is an improved technique for generating parity blocks which offers increased speed and efficiency. In this manner, the advantages of currently-existing high-speed CPUs and electronic memories may be fully exploited. Furthermore, a flexible parity generation scheme is required, which is adaptable to a wide variety of system applications and uses.
The present invention provides such a solution.